Robust Controller Design for Automatic Voltage Regulation
2020 American Control Conference (ACC)
In this paper, a robust controller is developed for an automatic voltage regulator (AVR) in power systems. In reality, the voltage at each substation fluctuates constantly due to disturbances. These voltage disturbances are mainly caused by load changes and loss of equipment. They degrade voltage/power quality, and if not corrected in time could lead to voltage collapse and black out. The AVR at generating stations is a crucial system to maintain the magnitude of terminal voltage at nominal value. But AVR itself is not robust enough against the disturbances. Therefore an additional controller is needed to improve the dynamic performance of the AVR and maintain the nominal voltage at each bus. An error driven active disturbance rejection controller (EDADRC) is originally designed and applied to enhance the performance of the AVR. In EDADRC, a feedback controller is constructed based on the difference between nominal and actual voltages. An observer is used to estimate the external disturbance, which is then compensated by the controller. The stability of EDADRC is theoretically proved. Both PID and EDADRC are implemented on a real time Simscape Electrical platform with actual power equipment. Simulation results demonstrate the superiority of the EDADRC to PID controller in disturbance rejection with comparable control efforts. They also verify the effectiveness of EDADRC in voltage regulation.
Mandali, Anusree; Dong, Lili; and Morinec, Allen, "Robust Controller Design for Automatic Voltage Regulation" (2020). Electrical Engineering & Computer Science Faculty Publications. 463.